PXD10RM Datasheet, PDF (659/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

bkn_fl_abort signal remains asserted until bkn_fl_done is driven high. For this setting, there are
no notification interrupts generated.
• Bn_RWWC = 0b100
— This setting provides the basic stall-while-write capability with the ability to abort any
program/erase operation if a read access is initiated plus the generation of an abort notification
interrupt. For this setting, the read request is captured and retried as described for the basic
stall-while-write, the program/erase operation is aborted by the PFLASH2P_LCA’s assertion
of the bkn_fl_abort signal and an abort notification interrupt generated. There are two abort
notification interrupts, one for each bank.
As detailed above, there are a total of 4 interrupt requests associated with the stall-while-write
functionality. These interrupt requests are captured as part of ECSM’s Interrupt Register and logically
summed together to form a single request to the interrupt controller.
Table 17-67. PFLASH2P_LCA Stall-While-Write Interrupts
MIR[n]
ECSM.MIR[7]
ECSM.MIR[6]
ECSM.MIR[5]
ECSM.MIR[4]
Interrupt Description
Platform flash bank0 abort notification, MIR[FB0AI]
Platform flash bank0 stall notification, MIR[FB0SI]
Platform flash bank1 abort notification, MIR[FB1AI]
Platform flash bank1 stall notification, MIR[FB1S1]
For example timing diagrams of the stall-while-write and abort-while-write operations, see Figure 17-51
and Figure 17-52 respectively.
17.4.4.12 Wait-State Emulation
Emulation of other memory array timings are supported by the PFLASH2P_LCA on read cycles to the
flash. This functionality may be useful to maintain the access timing for blocks of memory which were
used to overlay flash blocks for the purpose of system calibration or tuning during code development.
The PFLASH2P_LCA inserts additional wait-states according to the values of haddr[28:24]. When these
inputs are non-zero, additional cycles are added to AHB read cycles. Write cycles are not affected. In
addition, no page read buffer prefetches are initiated, and buffer hits are ignored.
Table 17-68 and Table 17-69 show the relationship of haddr[28:24] to the number of additional primary
wait-states. These wait-states are applied to the initial access of a burst fetch or to single-beat read accesses
on the AHB system bus.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
17-109