PXD10RM Datasheet, PDF (149/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

5.4.4.2 DMA Channel Select Register (DMAR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
31DMAR1 = Enable bits for channels 32 to 63 (extended internal channels)
DMAR2 = Enable bits for channels 64 to 95 (external channels)
Reset value: 0x0000_0000
Address: Base + 0x0048
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA}
W ^{63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48}
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA}
W ^{47 46 43 44 43 42 41 40 39 38 37 36 35 34 33 32}
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-16. DMA Channel Select Register 1 (DMAR1)
Address: Base + 0x004C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA}
W ^{95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80}
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA}
W ^{79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64}
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-17. DMA Channel Select Register 2 (DMAR2)
Table 5-16. DMA Channel Select Register (DMAR[1..2]) field descriptions
Field
31
n
Description
DMA0: DMA enable
When set (DMA0 = 1), channel 0 is enabled to transfer data in DMA mode.
DMAn: DMA enable
When set (DMAn = 1), channel n is enabled to transfer data in DMA mode.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
5-27