PXD10RM Datasheet, PDF (1251/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Field
0
NIF
1
NOVF
Table 41-3. NSR Field Descriptions
Description
NMI Status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (NREE or NFEE set),
NIF causes an interrupt request.
1 An event as defined by NREE and NFEE has occurred
0 No event has occurred on the pad
NMI Overrun Status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. It will be a copy of the current
NIF value whenever an NMI event occurs, thereby indicating to the software that an NMI occurred
while the last one was not yet serviced. If enabled (NREE or NFEE set), NOVF causes an interrupt
request.
1 An overrun has occurred on NMI input
0 No overrun has occurred on NMI input
41.4.2.2 NMI Configuration Register (NCR)
This register holds the configuration bits for the non-maskable interrupt settings.
Address:
0x0008
0
1
2
3
4
5
6
7
8
R _NLOC
WK
NDSS
0
0
NWRE
NREE NFEE NFE
Reset ₀
0
0
0
0
0
0
0
0
Access: User read/write
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 41-4. NMI Configuration Register (NCR)
Table 41-4. NCR Field Descriptions
Field
0
NLOCK
1-2
NDSS
3
NWRE[x]
Description
NMI Configuration Lock Register
Writing a 1 to this bit locks the configuration for the NMI until it is unlocked by a system reset. Writing
a 0 has no effect.
NMI Destination Source Select
00 Non-maskable interrupt
01 Critical interrupt
10 Machine check request
11 Reserved - no NMI, critical interrupt, or machine check request generated
NMI Wakeup Request Enable
1 A set NIF bit or set NOVF bit causes a system wakeup request
0 System wakeup requests from the corresponding NIF bit are disabled
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
41-5