PXD10RM Datasheet, PDF (1090/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

31.6.4 RTC Counter Register (RTCCNT)
The RTCCNT register contains the current value of the RTC counter.
Figure 31-6. RTC Counter Register (RTCCNT)
Offset: RTC_BASE + 0x000C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RTCCNT[0:31]
W
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 31-4. RTCCNT Register Bit/Field Descriptions
Field
Description
0:31
RTC Counter Value
RTCCNT[0:31] Due to the clock synchronization, the RTCCNT value may actually represent a previous counter
value.
31.7 RTC functional description
The RTC consists of a 32-bit free running counter enabled with the RTCC[CNTEN] bit (CNTEN when
negated asynchronously resets the counter and synchronously enables the counter when enabled). The
value of the counter may be read via the RTCCNT register. Note that due to the clock synchronization, the
RTCCNT value may actually represent a previous counter value. The difference between the counter and
the read value depends on ratio of counter clock and ipg_clk. Maximum possible difference between the
two is 6 count values.
The clock source to the counter is selected with the RTCC[CLKSEL] field, which gives four options for
clocking the RTC/API. The four clock sources are assumed to be two 16 MHz sources, one 32 kHz source
and one 128 kHz source. The output of the clock mux can be optionally divided by combination of 512
and 32 to give a 1 ms RTC/API count period for different clock sources. Note that the RTCC[CNTEN] bit
must be disabled when the RTC/API clock source is switched.
When the counter value for counter bits 10:21 match the 12-bit value in the RTCC[RTCVAL] field, then
the RTCS[RTCF] interrupt flag bit is set (after proper clock synchronization). If the RTCC[RTCIE]
interrupt enable bit is set, then the RTC interrupt request is generated. The RTC supports interrupt requests
in the range of 1s to 4096s (> 1 hr.) with a 1s resolution. The RTCC[RTCVAL] field may only be updated
when the RTCC[CNTEN] bit is cleared to disable the counter. If there is a match while in low power mode
then the RTC will first generate a wakeup request to force a wakeup to run mode, then the RTCF flag will
be set. RTCC[RTCVAL]=0x000 is invalid.
A rollover interrupt can be generated when the RTC transitions from a count of 0xFFFF_FFFF to
0x0000_0000. The rollover flag is enabled by setting the RTCC[ROVREN] bit. An interrupt request is
generated for an RTC counter rollover when both the RTCC[ROVREN] and RTCC[RTCIE] bits are set.
All the flags and counter values are synchronized with ipg_clk. It is assumed that ipg_clk frequency is
always more than or equal to the rtc_clk used to run the counter.
31-8
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor