PXD10RM Datasheet, PDF (547/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

16.4.2.18 RAM ECC Attributes (REAT) register
The REAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled
ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event
in the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-17 and Table 16-19 for the RAM ECC Attributes Register definition.
Register address: ECSM Base + 0x67
0
1
2
3
4
5
6
7
R
Write
Size[0:2]
Protection[0:3]
W
RESET:
x
x
x
x
x
x
x
x
= Unimplemented
Figure 16-17. RAM ECC Attributes (REAT) Register
Table 16-19. RAM ECC Attributes (REAT) Field Descriptions
Name
Description
0
Write
AMBA-AHB HWRITE
0 = AMBA-AHB read access
1 = AMBA-AHB write access
1-3
Size[0:2]
AMBA-AHB HSIZE[0:2]
0b000 = 8-bit AMBA-AHB access
0b001 = 16-bit AMBA-AHB access
0b010 = 32-bit AMBA-AHB access
0b1xx = Reserved
4-7
Protection[0:3]
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable
Protection[2]: Bufferable 0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
16.4.2.19 RAM ECC Data Register (REDR)
The REDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the
RAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 16-18 and Table 16-20 for the RAM ECC Data Register definition.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
16-21