PXD10RM Datasheet, PDF (1075/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Bus related command. The QSPI_SFMFR[IPIEF] flag is asserted when the host tries to trigger an IP Bus
related command. When the host triggers an AHB Bus related command (refer to Section 30.5.3.3.1,
Reading Serial Flash Data into the QuadSPI Module” for details) this command is stalled until the
currently running IP Bus related command is finished.
During the execution of an AHB Bus related command the running command can’t be terminated by
issuing an IP Bus related command. The command is ignored and the QSPI_SFMFR[IPAEF] flag is
asserted. Refer to Section 30.4.3.20, Serial Flash Mode Flag Register (QSPI_SFMFR)” for the description
of these flags.
When another AHB Bus related command is triggered the address of the memory mapped access is
considered. If the requested address is currently read from the serial flash device the running command is
continued. If this is not the case the currently running command is terminated and another AHB Bus
related command related to the requested address is executed. Refer to Section 30.5.3.3.1, Reading Serial
Flash Data into the QuadSPI Module” for further details.
The commands ignored in case of command collision will not result in the assertion of the
QSPI_SFMFR[TFF] flag. It’s up to the application to watch the error flags provided to assign the
assertions of the TFF flag to the appropriate commands.
30.6.8 DMA Usage
For the complete description of the DMA module refer to the related chapter. In this paragraph only the
details specific to the DMA usage related to the QuadSPI module are given.
30.6.8.1 DMA Usage in SPI Slave Mode
30.6.8.1.1 DMA Setup in SPI Slave Mode
When using the DMA in the SPI Slave Mode the standard IP DMA interface protocol is used. For proper
operation the DMA controller must be set up in the following way:
• Size of the source minor loop must be set to 2, corresponding to the width of the
QSPI_POPR[RXDATA] field.
• Size of the source major loop must be set to the number of bytes which are expected from the SPI
Master.
• Source address must be set to the address of the QSPI_POPR register.
• Source address increment must be set to 0.
• Remaining DMA controller setup depends from the application.
30.6.8.2 DMA Usage in SFM Mode
30.6.8.2.1 Bandwidth Considerations in SFM Mode
Careful consideration of the throughput rate of the entire chain (serial flash -> AHB bus -> DMA
controller) involved in the read data process is essential for proper operation. Such analysis must take into
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-71