PXD10RM Datasheet, PDF (317/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

11.8.5.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in Figure 11-14 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SIN_x pins on the odd-numbered SCK_x edges and change the data on their SOUT_x pins on the
even-numbered SCK_x edges.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master and slave
sample
Master SOUT /
Slave SIN
Master SIN /
Slave SOUT
Master (CPHA = 0): TCF and EOQF are set and RXCTR counter
is updated at next to last SCK edge of frame (edge 15)
Slave (CPHA = 0): TCF is set and RXCTR counter is updated at
last SCK edge of frame (edge 16)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PCSx / SS
t_CSC
MSB first (LSBFE = 0): MSB Bit 6 Bit 5
LSB first (LSBFE = 1): LSB Bit 1 Bit 2
t_CSC = CSCS to SCK delay.
t_ASC = After SCK delay.
t_DT = Delay after transfer (minimum CS idle time).
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
t_ASC
t_DT
LSB ^tCSC
MSB
Figure 11-14. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
The master initiates the transfer by placing its first data bit on the SOUT_x pin and asserting the
appropriate peripheral chip select signals to the slave device. The slave responds by placing its first data
bit on its SOUT_x pin. After the t_CSC delay has elapsed, the master outputs the first edge of SCK_x. This
is the edge used by the master and slave devices to sample the first input data bit on their serial data input
signals. At the second edge of the SCK_x the master and slave devices place their second data bit on their
serial data output signals. For the rest of the frame the master and the slave sample their SIN_x pins on the
odd-numbered clock edges and changes the data on their SOUT_x pins on the even-numbered clock edges.
After the last clock edge occurs a delay of t_ASC is inserted before the master negates the CS signals. A
delay of t_DT is inserted before a new frame transfer can be initiated by the master.
For the CPHA = 0 condition of the master, TCF and EOQF are set and the RXCTR counter is updated at
the next to last serial clock edge of the frame (edge 15) of Figure 11-14.
For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial
clock edge of the frame (edge 16) of Figure 11-14.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-35