PXD10RM Datasheet, PDF (512/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

DMA
addr
wdata[31:0]
DMA engine
hrdata[{63,31}:0]
data_path
SRAM
Transfer
Control
Descriptor (TCD)
pmodel_charb
addr_path
c
o
n
t
r
o
l
0
j
j+1
n-1
rdata[31:0]
IPS
Bus
AMBA
Bus
hwdata[{63,31}:0]
haddr[31:0]
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 15-29. DMA operation, part 2
Once the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the addr_path logic performs the required updates to certain fields in the channel’s TCD, e.g.,
saddr, daddr, citer. If the outer major iteration count is exhausted, then there are additional operations
which are performed. These include the final address adjustments and reloading of the biter field into the
citer. Additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of
a new TCD from memory using the scatter/gather address pointer included in the descriptor. The updates
to the TCD memory and the assertion of an interrupt request are shown in Figure 15-30.
15-42
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor