PXD10RM Datasheet, PDF (478/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

For more details, consult Section 15.2.1, Register descriptions, and Section 15.3, Functional description.
15.2 Memory map/register definition
The DMA’s programming model is partitioned into two sections, both mapped into the slave bus space:
the first region defines a number of registers providing control functions, while the second region
corresponds to the local transfer control descriptor memory.
Reading an unimplemented register bit or memory location will return the value of zero. Write the value
of zero to unimplemented register bits. Any access to a reserved memory location will result in a bus error.
Reserved memory locations are indicated in the memory map. For 16- and 32-channel implementations,
reserved memory also includes the high order "H" registers containing channels 63-32 data (i.e.,
DMAERQH, DMAEEIH, DMAINTH, DMAERRH).
Many of the control registers have a bit width that matches the number of channels implemented in the
module, i.e., 16-, 32- or 64-bits in size. Registers associated with a 64-channel design are implemented as
two 32-bit registers, and include an “H” and “L” suffixes, signaling the “high” and “low” portions of the
control function. The descriptions in this section define the 64-channel implementation. For 16- or
32-channel designs, the unused bits are not implemented: reads return zeroes, and writes are ignored.
The DMA module does not include any logic which provides access control. Rather, this function is
supported using the standard access control logic provided by the PBRIDGE controller.
Table 15-1 is a 32-bit view of the DMA’s memory map.
Table 15-1. DMA 32-bit memory map
DMA Offset
0x0000
0x0004
0x0008
0x000c
0x0010
0x0014
0x0018
0x001c
0x0020
0x0024
0x0028
0x002c
0x0030
0x0034
0x0038
0x003c-0x00fc
Register
DMA Control Register (DMACR)
DMA Error Status (DMAES)
DMA Enable Request High (DMAERQH, Channels 63-32)
DMA Enable Request Low (DMAERQL, Channels 31-00)
DMA Enable Error Interrupt High (DMAEEIH, Channels 63-32)
DMA Enable Error Interrupt Low (DMAEEIL, Channels 31-00)
DMA Set Enable
Request
(DMASERQ)
DMA Clear Enable
Request
(DMACERQ)
DMA Set Enable
Error Interrupt
(DMASEEI)
DMA Clear Enable
Error Interrupt
(DMACEEI)
DMA Clear Interrupt
Request
(DMACINT)
DMA Clear
Error
(DMACERR)
DMA Set Start Bit
(DMASSRT)
DMA Clear Done
Status Bit
(DMACDNE)
DMA Interrupt Request High (DMAINTH, Channels 63-32)
DMA Interrupt Request Low (DMAINTL, Channels 31-00)
DMA Error High (DMAERRH, Channels 63-32)
DMA Error Low (DMAERRL, Channels 31-00)
DMA Hardware Request Status High (DMAHRSH, Channels 63-32)
DMA Hardware Request Status Low (DMAHRSL, Channels 31-00)
DMA General Purpose Output Register (DMAGPOR)
Reserved
15-8
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor