PXD10RM Datasheet, PDF (741/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 20-8. IBCR Field Descriptions (continued)
Field
Description
RSTA
Repeat Start. Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the
current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if
the bus is owned by another master, will result in loss of arbitration.
1 Generate repeat start cycle
0 No effect
DMAEN
DMA Enable. When this bit is set, the DMA TX and RX lines will be asserted when the I²C module requires
data to be read or written to the data register. No Transfer Done interrupts will be generated when this bit
is set, however an interrupt will be generated if the loss of arbitration or addressed as slave conditions
occur. The DMA mode is only valid when the I²C module is configured as a Master and the DMA transfer
still requires CPU intervention at the start and the end of each frame of data. See the DMA Application
Information section for more details.
1 Enable the DMA TX/RX request signals
0 Disable the DMA TX/RX request signals
IBSDOZ I-Bus Interface Stop in DOZE mode.
E 1 Halt I²C Bus module clock generation (if DOZE mode signal asserted)
0 I²C Bus module clock operates normally
Note: If the IBSDOZE mode is SET, the I²C module will enter DOZE mode when the DOZE signal is
asserted, if there are no current transactions on the bus. The I²C module would then signal to the
system that the clock can be shut down.
Note: If it were the case that the IBDOZE bit was cleared when the DOZE signal was asserted, the I²C
Bus module clock would remain alive, and any current transactions would continue as normal.
20.4.3.4 I²C Bus Status Register
Offset 0x0003
Access: Read-only any time¹
0
1
2
3
4
5
R TCF
IAAS
IBB
IBAL
0
SRW
W
w1c
Reset
1
0
0
0
0
0
Figure 20-8. I²C Bus Status Register (IBSR)
1 _{With the exception of IBIF and IBAL, which are software clearable.}
6
7
IBIF
RXAK
w1c
0
0
Table 20-9. IBSR Field Descriptions
Field
Description
TCF Transfer complete. While one byte of data is being transferred, this bit is cleared. It is set by the falling edge
of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer
to the I²C module or from the I²C module.
1 Transfer complete
0 Transfer in progress
IAAS
Addressed as a slave. When its own specific address (I-Bus Address Register) is matched with the calling
address, this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU needs to check the
SRW bit and set its Tx/Rx mode accordingly. Writing to the I-Bus Control Register clears this bit.
1 Addressed as a slave
0 Not addressed
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
20-11