PXD10RM Datasheet, PDF (815/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 22-26. LCDRAM (Location 15) Field Descriptions
Field
0:31 FP[60:63]BP[5:0]. LCD segment ON.
Description
The FP[60:63]BP[5:0] bit displays (turns on) the LCD segment connected between FP[60:63] and BP[5:0].
1 = LCD segment ON
0 = LCD segment OFF.
22.5 Functional Description
22.5.1 Frontplane, Backplane, and LCD System During Reset
During a reset the following conditions exist:
• All frontplane enable bits, FP[n-1:0]EN are cleared and the ON/OFF control for the display, the
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The pin state during reset is defined by the port control module.
• The LCD64F6B system is configured in the default mode, 1/1 duty and 1/1 bias, that means only
BP0 is used, system clock as reference, VLCD pin not used as voltage reference.
22.5.2 LCD Clock and Frame Frequency
The frequency of the clock and the clock divider determine the LCD Clock Frequency. The input clock for
the prescaler can be selected by LCDRCS bit. The divider is set by the LCD Clock Prescaler bits, in the
LCD Prescaler Control Register according to Table 22-27.
Table 22-27. Clock Divider
LCLK
Divider
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
480
2 * 480
2² * 480
2³ * 480
2⁴ * 480
2⁵ * 480
2⁶ * 480
2⁷ * 480
2⁸ * 480
2⁹ * 480
2¹⁰ * 480
2¹¹ * 480
2¹² * 480
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
22-29