PXD10RM Datasheet, PDF (1232/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 39-1. STM memory map
Address
Offset
Register Name
Register Description
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C -
0x3FFF
STM_CR
STM_CNT
STM_CCR0
STM_CIR0
STM_CMP0
STM_CCR1
STM_CIR1
STM_CMP1
STM_CCR2
STM_CIR2
STM_CMP2
STM_CCR3
STM_CIR3
STM_CMP3
-
STM Control Register
STM Counter Value
Reserved
Reserved
STM Channel 0 Control Register
STM Channel 0 Interrupt Register
STM Channel 0 Compare Register
Reserved
STM Channel 1 Control Register
STM Channel 1 Interrupt Register
STM Channel 1 Compare Register
Reserved
STM Channel 2 Control Register
STM Channel 2 Interrupt Register
STM Channel 2 Compare Register
Reserved
STM Channel 3 Control Register
STM Channel 3 Interrupt Register
STM Channel 3 Compare Register
Reserved
Size
(bits)
Access
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
-
-
Location
on page 2
on page 3
on page 4
on page 4
on page 5
on page 4
on page 4
on page 5
on page 4
on page 4
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on page 4
on page 4
on page 5
39.3.2 Register descriptions
The following sections detail the individual registers within the STM programming model.
Figure 39-1 shows the conventions used in the register figures.
Always 1 Always 0 R/W BIT Read- BIT Write-
Write 1 BIT Self-clear 0 N/A
reads 1
reads 0
bit
only bit
only bit _BIT to clear _w1c
bit _BIT
Figure 39-1. Key to register fields
39.3.2.1 STM Control Register (STM_CR)
The STM Control Register (STM_CR) includes the prescale value, freeze control and timer enable bits.
39-2
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor