PXD10RM Datasheet, PDF (706/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

updated. In order to avoid this situation, the abort procedures described in Section 18.4.6.1,
Transmission Abort Mechanism should be used.
18.4.6.3 Message Buffer Lock Mechanism
Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive process. When
the CPU reads the Control and Status word of an “active not empty” Rx MB, FlexCAN assumes that the
CPU wants to read the whole MB in an atomic operation, and thus it sets an internal lock flag for that MB.
The lock is released when the CPU reads the Free Running Timer (global unlock operation), or when it
reads the Control and Status word of another MB. The MB locking is done to prevent a new frame to be
written into the MB while the CPU is reading it.
NOTE
The locking mechanism only applies to Rx MBs which have a code different
than INACTIVE (‘0000’) or EMPTY¹ (‘0100’). Also, Tx MBs can not be
locked.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the array are
programmed with the same ID, and FlexCAN has already received and stored messages into these two
MBs. Suppose now that the CPU decides to read MB number 5 and at the same time another message with
the same ID is arriving. When the CPU reads the Control and Status word of MB number 5, this MB is
locked. The new message arrives and the matching algorithm finds out that there are no “free to receive”
MBs, so it decides to override MB number 5. However, this MB is locked, so the new message can not be
written there. It will remain in the SMB waiting for the MB to be unlocked, and only then will be written
to the MB. If the MB is not unlocked in time and yet another new message with the same ID arrives, then
the new message overwrites the one on the SMB and there will be no indication of lost messages either in
the Code field of the MB or in the Error and Status Register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code field is asserted.
If the CPU reads the Control and Status word and finds out that the BUSY bit is set, it should defer
accessing the MB until the BUSY bit is negated.
NOTE
If the BUSY bit is asserted or if the MB is empty, then reading the Control
and Status word does not lock the MB.
Deactivation takes precedence over locking. If the CPU deactivates a locked Rx MB, then its lock status
is negated and the MB is marked as invalid for the current matching round. Any pending message on the
SMB will not be transferred anymore to the MB.
18.4.7 Rx FIFO
The receive-only FIFO is enabled by asserting the FEN bit in the MCR. The reset value of this bit is zero
to maintain software backwards compatibility with previous versions of the module that did not have the
FIFO feature. When the FIFO is enabled, the memory region normally occupied by the first 8 MBs
1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honoured when
the BCC bit is negated.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor