PXD10RM Datasheet, PDF (153/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 5-19. Conversion timing registers CTR[1..2] field descriptions (continued)
Field
24:31
Description
INPSAMP[0:7]
Configuration bits for sampling phase duration
5.4.7 Mask registers
5.4.7.1 Introduction
These registers are used to program which of the 96 input channels must be converted during Normal and
Injected conversion.
5.4.7.2 Normal Conversion Mask Registers (NCMR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
NCMR1 = Enable bits of normal sampling for channel 32 to 63 (extended internal channels)
Reset value: 0x0000_0000
Address: Base + 0x00A8
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CH63 CH62 CH61 CH60 CH59 CH58 CH57 CH56 CH55 CH54 CH53 CH52 CH51 CH50 CH49 CH48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CH47 CH46 CH45 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-21. Normal Conversion Mask Register 1 (NCMR1)
Table 5-20. Normal Conversion Mask Registers (NCMR[1..2]) field descriptions
Field
31
n
Description
CH0: Sampling enable
When set Sampling is enabled for channel 0.
CHn: Sampling enable
When set Sampling is enabled for channel n.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
5-31