PXD10RM Datasheet, PDF (261/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

If when entering OPWFMB mode coming out from GPIO mode the internal counter value is not within
that range then the B match will not occur causing the channel internal counter to wrap at the maximum
counter value which is 0xFFFF for a 16-bit counter. After the counter wrap occurs it returns to 0x1 and
resume normal OPWFMB mode operation. Thus in order to avoid the counter wrap condition make sure
its value is within the 0x1 to B1 register value range when the OPWFMB mode is entered.
When a match on comparator A occurs the output register is set to the value of EDPOL. When a match on
comparator B occurs the output register is set to the complement of EDPOL. B1 match also causes the
internal counter to transition to 0x1, thus restarting the counter cycle.
Only values greater than 0x1 are allowed to be written to B1 register. Loading values other than those leads
to unpredictable results.
Figure 9-29 describes the operation of the OPWFMB mode regarding output pin transitions and A1/B1
registers match events. Note that the output pin transition occurs when the A1 or B1 match signal is
deasserted which is indicated by the A1 match negedge detection signal. If register A1 is set to 0x4 the
output pin transitions 4 counter periods after the cycle had started, plus one system clock cycle. Note that
in the example shown in Figure 9-29 the internal counter prescaler has a ratio of two.
system clock
prescaler
EMIOSCNT
1
A1 value
B1 value
A1 match
0x000004
0x000008
A1 match negedge detection
B1 match
8
5
4
match A1 negedge detection
TIME
match B1 negedge detection
Prescaler ratio = 2
B1 match negedge detection
output pin
EDPOL = 0
Figure 9-29. OPWFMB A1 and B1 match to Output Register Delay
Figure 9-30 describes the generated output signal if A1 is set to 0x0. Since the counter does not reach zero
in this mode, the channel internal logic infers a match as if A1=0x1 with the difference that in this case,
the posedge of the match signal is used to trigger the output pin transition instead of the negedge used when
A1=0x1. Note that A1 posedge match signal from cycle n+1 occurs at the same time as B1 negedge match
signal from cycle n. This allows to use the A1 posedge match to mask the B1 negedge match when they
occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty cycle
is generated.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-35