PXD10RM Datasheet, PDF (1067/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

While the clocks are shut off, the QuadSPI memory-mapped logic is not accessible. The states of the
interrupt and DMA request signals cannot be changed while in Stop Mode.
Note that the following actions are illegal in SFM Mode during the time starting with raising the request
to enter Stop Mode and ending with leaving the Stop Mode:
• Issue a new SFM command
• Issue a new AHB request
30.5.4.2 Module Disable Mode
Module Disable Mode is a block-specific mode that the QuadSPI can enter to save power. There are two
possibilities to request entering the Module Disable Mode:
• Host software can initiate the Module Disable Mode by writing a ‘1’ to the MDIS bit in the
QSPI_MCR.
• The Module Disable Mode can also be initiated by hardware. A power management block can
initiate Module Disable Mode by asserting the ipg_doze signal while the DOZE bit in the
QSPI_MCR is asserted.
When a request is encountered to enter the Module Disable Mode the QuadSPI negates ipg_enable_clk
when it is ready to enter the Module Disable Mode. Depending from the mode of operation the following
conditions must be met for the negation of ipg_enable_clk:
• If a serial transfer is in progress in one of the SPI Modes the QuadSPI waits until it reaches the
frame boundary before negating ipg_enable_clk.
• If a SFM command is currently executed in SFM Mode the negation of ipg_enable_clk is
postponed until this command is finished.
Note that there is only a limited possibility to read back whether the QuadSPI block is waiting for the
completion of these conditions or whether it has already negated the ipg_enable_clk. The host software
can read the QSPI_SFMSR[BUSY] bit to check for pending execution of a SFM command, but there is
no possibility to check pending DMA or CPU read requests on the AHB Buffer.
If implemented, the ipg_enable_clk signal can stop the clock to the non-memory mapped logic. When
ipg_enable_clk is negated, the QuadSPI is in a dormant state, but the memory mapped registers are still
accessible. Certain read or write operations have a different effect when the QuadSPI is in the Module
Disable Mode. Clearing either of the FIFOs will not have any effect in the Module Disable Mode. In the
Module Disable Mode, all status bits and register flags in the QuadSPI will return the correct values when
read, but writing to them will have no effect. Writing to the QSPI_TCR during Module Disable Mode will
not have any effect. Interrupt and DMA request signals cannot be cleared while in the Module Disable
Mode.
It is not allowed to write to the FIFO registers in this mode.
Note that the following actions are illegal in SFM Mode during the time starting with raising the request
to enter Module Disable Mode and ending with leaving the Module Disable Mode:
• Issue a new SFM command
• Issue a new AHB request
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-63