PXD10RM Datasheet, PDF (479/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 15-1. DMA 32-bit memory map (continued)
DMA Offset
Register
0x0100
0x0104
0x0108
0x010c
0x0110
0x0114
0x0118
DMA Channel 0
Priority (DCHPRI0)
DMA Channel 4
Priority (DCHPRI4)
DMA Channel 8
Priority (DCHPRI8)
DMA Channel 12
Priority (DCHPRI12)
DMA Channel 16
Priority (DCHPRI16)
DMA Channel 20
Priority (DCHPRI20)
DMA Channel 24
Priority (DCHPRI24)
DMA Channel 1
Priority (DCHPRI1)
DMA Channel 5
Priority (DCHPRI5)
DMA Channel 9
Priority (DCHPRI9)
DMA Channel 13
Priority (DCHPRI13)
DMA Channel 17
Priority (DCHPRI17)
DMA Channel 21
Priority (DCHPRI21)
DMA Channel 25
Priority (DCHPRI25)
DMA Channel 2
Priority (DCHPRI2)
DMA Channel 6
Priority (DCHPRI6)
DMA Channel 10
Priority (DCHPRI10)
DMA Channel 14
Priority (DCHPRI14)
DMA Channel 18
Priority (DCHPRI18)
DMA Channel 22
Priority (DCHPRI22)
DMA Channel 26
Priority (DCHPRI26)
DMA Channel 3
Priority (DCHPRI3)
DMA Channel 7
Priority (DCHPRI7)
DMA Channel 11
Priority (DCHPRI11)
DMA Channel 15
Priority (DCHPRI15)
DMA Channel 19
Priority (DCHPRI19)
DMA Channel 23
Priority (DCHPRI23)
DMA Channel 27
Priority (DCHPRI27)
0x011c
0x0120
0x0124
0x0128
0x012c
0x0130
0x0134
0x0138
0x013c
DMA Channel 28
Priority (DCHPRI28)
DMA Channel 32
Priority (DCHPRI32)
DMA Channel 36
Priority (DCHPRI36)
DMA Channel 40
Priority (DCHPRI40)
DMA Channel 44
Priority (DCHPRI44)
DMA Channel 48
Priority (DCHPRI48)
DMA Channel 52
Priority (DCHPRI52)
DMA Channel 56
Priority (DCHPRI56)
DMA Channel 60
Priority (DCHPRI60)
DMA Channel 29
Priority (DCHPRI29)
DMA Channel 33
Priority (DCHPRI33)
DMA Channel 37
Priority (DCHPRI37)
DMA Channel 41
Priority (DCHPRI41)
DMA Channel 45
Priority (DCHPRI45)
DMA Channel 49
Priority (DCHPRI49)
DMA Channel 53
Priority (DCHPRI53)
DMA Channel 57
Priority (DCHPRI57)
DMA Channel 61
Priority (DCHPRI61)
DMA Channel 30
Priority (DCHPRI30)
DMA Channel 34
Priority (DCHPRI34)
DMA Channel 38
Priority (DCHPRI38)
DMA Channel 42
Priority (DCHPRI42)
DMA Channel 46
Priority (DCHPRI46)
DMA Channel 50
Priority (DCHPRI50)
DMA Channel 54
Priority (DCHPRI54)
DMA Channel 58
Priority (DCHPRI58)
DMA Channel 62
Priority (DCHPRI62)
DMA Channel 31
Priority (DCHPRI31)
DMA Channel 35
Priority (DCHPRI35)
DMA Channel 39
Priority (DCHPRI39)
DMA Channel 43
Priority (DCHPRI43)
DMA Channel 47
Priority (DCHPRI47)
DMA Channel 51
Priority (DCHPRI51)
DMA Channel 55
Priority (DCHPRI55)
DMA Channel 59
Priority (DCHPRI59)
DMA Channel 63
Priority (DCHPRI63)
0x0140-0x0ffc
0x1000-0x11fc
0x1200-0x13fc
0x1400-0x15fc
0x1600-0x17fc
Reserved
TCD00-TCD15
TCD16-TCD31
TCD32-TCD47
TCD48-TCD63
15.2.1 Register descriptions
15.2.1.1 DMA Control Register (DMACR)
The 32-bit DMACR defines the basic operating configuration of the DMA.
The DMA arbitrates channel service requests in groups of 16 channels. The 64- and 32-channel
configurations have four groups (3,2,1,0) and two groups (1,0), respectively; the 16 channel configuration
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
15-9