PXD10RM Datasheet, PDF (537/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 16-9. ECC Status (ESR) Field Descriptions
Name
2
R1BC
Description
RAM 1-bit Correction
0 = No reportable single-bit RAM correction has been detected.
1 = A reportable single-bit RAM correction has been detected.
3
F1BC
This bit can only be set if ECR[EPR1BR] is asserted. The occurrence of a properly-enabled single-bit
RAM correction generates a ECSM ECC interrupt request. The address, attributes and data are also
captured in the REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1
to this bit. Writing a 0 has no effect.
Flash 1-bit Correction
0 = No reportable single-bit flash correction has been detected.
1 = A reportable single-bit flash correction has been detected.
6
RNCE
This bit can only be set if ECR[EPF1BR] is asserted. The occurrence of a properly-enabled single-bit
flash correction generates a ECSM ECC interrupt request. The address, attributes and data are also
captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this
bit. Writing a 0 has no effect.
RAM Non-Correctable Error
0 = No reportable non-correctable RAM error has been detected.
1 = A reportable non-correctable RAM error has been detected.
7
FNCE
The occurrence of a properly-enabled non-correctable RAM error generates a ECSM ECC interrupt
request. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT
and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
Flash Non-Correctable Error
0 = No reportable non-correctable flash error has been detected.
1 = A reportable non-correctable flash error has been detected.
The occurrence of a properly-enabled non-correctable flash error generates a ECSM ECC interrupt
request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and
FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
In the event that multiple status flags are signaled simultaneously, ECSM records the event with the R1BC
as highest priority, then F1BC, then RNCE, and finally FNCE.
16.4.2.10 ECC Error Generation Register (EEGR)
The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided
for two purposes:
• It provides a software-controlled mechanism for “injecting” errors into the memories during data
writes to verify the integrity of the ECC logic.
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash,
i.e., the ability to program the non-volatile memory with single- or double-bit errors is supported for the
same two reasons previously identified.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
16-11