PXD10RM Datasheet, PDF (533/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Register address: ECSM Base + 0x24
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
MUDCR[0:15]
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MUDCR[16:31]
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-6. Miscellaneous User-Defined Control (MUDCR) Register
Table 16-7. Miscellaneous User-Defined Control Register (MUDCR) Field Descriptions
Name
MUDCR
Description
User-Defined control Register
0 = The control associated with this MUDCR bit is disabled.
1 = The control associated with this MUDCR bit is enabled.
16.4.2.6.1 AXBS_lite force_round_robin bit (MUDCR[31])
When the AXBS_lite is included on the platform, this bit is used to drive the force_round_robin bit of the
AXBS_lite. This will force the slaves into round robin mode of arbitration rather than fixed mode. Unless
a master is using priority elevation, which forces the design back into fixed mode regardless of this bit. By
defining the ‘define ENABLE_ROUND_ROBIN_RESET, this bit will reset to 1.
16.4.2.7 ECC registers
For designs including error-correcting code (ECC) implementations to improve the quality and reliability
of memories, there are a number of program-visible registers for the sole purpose of reporting and logging
of memory failures. These optional registers include:
• ECC Configuration Register (ECR)
• ECC Status Register (ESR)
• ECC Error Generation Register (EEGR)
• Flash ECC Address Register (FEAR)
• Flash ECC Master Number Register (FEMR)
• Flash ECC Attributes Register (FEAT)
• Flash ECC Data Register (FEDR)
• RAM ECC Address Register (REAR)
• RAM ECC Syndrome Register (RESR)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
16-7