PXD10RM Datasheet, PDF (1178/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Cosine Coil
Sine Coil
VDDM
VDDM
T1
COSP
P
A
S1
D
S2
T2
T3
COSM
P
S3
A
D
S4
T4
VDDM
VDDM
T5
SINP
P
A
S5
D
S6
T6
T7
SINM
P
S7
A
D
S8
T8
OBE to pads
VSSM
reference
integrator
VSSM
C1
VSSM
DAC
VSSM
Bus
Clock
R1
–
–
+
VDDM
+
R2
+
–
R2
VSSM
sigma-delta modulator + ref. voltage generation
Offset
DFF
Cancellation
Accumulator
Prescaler
Integration
Accumulator
SSD_1MOT analog block
Down Counter
Load Register
Clock signals
Down Counter
Prescaler
Shaded Down Counter Blocks:
Separate for Blanking and Integration
Down Counter
BIS
Control
Figure 36-10. SSD Block Diagram, Analog Block
Main part of the analog block is the -modulator. It is operational during the BIS integration phase only
(step 5 in Section 36.4.2.2, Details of the SSD Measurement”). The clock to update the feedback path is
derived from the bus clock using the ACDIV setting. The 1-bit output value provided to the digital part is
used to increment or decrement the ITGACC register.
36-12
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor