PXD10RM Datasheet, PDF (211/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

• Frequency modulated PLL
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth
— ±0.25% to ±4% deviation from center spread frequency
— -0.5% to +8% deviation from down spread frequency
— Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
• Five available modes
— Normal mode
— Progressive clock switching
— Normal Mode with FM
— Powerdown mode
— 1:1 mode (FMPLL0 only)
8.9.4 Memory map¹
Table 8-22 shows the memory map locations. Addresses are given as offsets of the module base address.
Table 8-22. FMPLL Memory Map
Address
Base:
0xC3FE00A0 (FMPLL0)
0xC3FE00C0 (FMPLL1)
0x0000
0x0004
Register
Control register (CR)
Modulation register (MR)
Access Location
R/W
Special
on page 34
on page 36
8.9.5 Register description
The PLL operation is controlled by two registers. Those registers can only be written in supervisor mode.
1.FMPLL_x are mapped through the ME_CGM Register Slot
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-33