PXD10RM Datasheet, PDF (1182/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Any write access on byte-level is ignored.
All reserved registers provide 0x0000 on read. Write access is not allowed.
36.4.1.4 BIS Control
Once triggered the sequence control logic walks through a single individual BIS. In the normal application
one BIS corresponds to a single step (90 movement of the SM). In detail the BIS is implemented in the
SSD block in the following way:
• Each BIS starts with setting the TRIG bit. Ending a running BIS manually is only possibly by
clearing the RTZE bit.
• If the BLNCNTLD register is set to a value other than 0x0000 the DCNT is loaded with
(BLNCNTLD - 1) and is started using the BLNDIV bit setting for the clock divider. The BLNST
is set.
The blanking phase of the BIS is executed, the BLNDCL bit is used to determine whether one of
the coils is driven during the blanking phase.
If the appropriate number of down counter periods (equal to the BLNCNTLD register value)
expires the BLNIF is set, the interrupt is triggered according to the BLNIE bit and the BLNST bit
is cleared.
• If the ITGCNTLD register is set to a value other than 0x0000 the DCNT is loaded with
(ITGCNTLD - 1) and is started using the ITGDIV bit setting for the clock divider. The ITGST is
set and the ITGACC register is initialized with 0x0000.
The integration phase of the BIS is executed, the ITGDCL bit is used to determine whether one of
the coils is driven during the integration phase. The -modulator of the analog block is functional
and the ITGACC register is updated. During the integration phase the polarity is switched
according to the OFFCNC bits.
If the appropriate number of down counter periods (equal to the ITGCNTLD register value) expires
the ITGIF is set, the interrupt is triggered according to the ITGIE bit and the ITGST bit is cleared.
The state of the ongoing BIS can be monitored by the following status bits:
• The BLNST bit is set during the blanking phase exclusively.
• The ITGST bit is set during the integration phase exclusively. When it is set, the BIS control
enables the -modulator in the analog block together with the integration circuitry. As long as the
integration phase is active the ITGACC register content is modified depending from the output of
the -modulator.
In the normal use case the end of the BIS is the end of the integration phase. Independent from the time
required by the software to detect and act upon the end of the BIS the ITGACC register is not changed
after the end of the integration phase.
The sequence control logic itself makes use of the following sub blocks:
36.4.1.4.1 Down Counter
The down counter is basically a timer with the divider factor (BLNDIV or ITGDIV) and length
(BLNCNTLD or ITGCNTLD) determined by the current state of the BIS. Additionally to defining the
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor