PXD10RM Datasheet, PDF (260/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

internal counter
0x000008
0x000006
0x000004
0x000002
0x000001
Counter = A1
cycle n
write to A2
Match A1
8
cycle n+1
Match A1
write to A2
4
cycle n+2
Match A1
6
Time
A1 load signal
A1 value 0x000008
A2 value 0x000008
0x000004
0x000004
0x000006
0x000006
Prescaler ratio = 2
Figure 9-27. MCB Mode A1 Register Update in Up Counter Mode
Figure 9-28 describes the A1 register update in up/down counter mode. Note that A2 can be written at any
time within cycle n in order to be used in cycle n+1. Thus A1 receives this new value at the next cycle
boundary. Note that the update disable bits OU[n] of EMIOSOUDIS register can be used to disable the
update of A1 register.
EMIOSCNT[n]
0x000006
0x000005
cycle n
match A1
write to A2
cycle n+1
write to A2
match A1
cycle n+2
0x000001
TIME
Counter = 2
A1 load signal
A1 value 0x000006
A2 value 0x000006
0x000005
0x000005
0x000006
0x000006
Prescaler ratio = 2
Figure 9-28. MCB Mode A1 Register Update in Up/Down Counter Mode
9.5.1.1.5 Output Pulse Width and Frequency Modulation Buffered (OPWFMB) Mode
This mode (MODE[0:6]=10110b0) provides waveforms with variable duty cycle and frequency. The
internal channel counter is automatically selected as the time base when this mode is selected. A1 register
indicates the duty cycle and B1 register the frequency. Both A1 and B1 registers are double buffered to
allow smooth signal generation when changing the registers values on the fly. 0% and 100% duty cycles
are supported.
At OPWFMB mode entry the output flip-flop is set to the value of the EDPOL bit in the EMIOSC[n]
register.
9-34
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor