PXD10RM Datasheet, PDF (1208/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

37.5.3.9 Pad Selection for Multiplexed Inputs Registers (PSMI0_3 - PSMI40_42)
Via routing it is possible to define different pads to be possible inputs for a certain peripheral function.
Address: Base + 0x0500 - 0x0528 (11 registers)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₀
0
0
0
W
PADSEL0
0
0
0
0
PADSEL1
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
W
PADSEL2
0
0
0
0
PADSEL3
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 37-12. Pad Selection for Multiplexed Inputs Register (PSMI0_3)
Table 37-11. PSMI0_3 Field Descriptions
Field
Description
PADSEL0 - 3,
PADSEL4 - 7,
...
PADSEL28 - 31
Pad Selection Bits
Each PADSEL field selects the pad currently used for a certain input function. See Table 37-12.
In order to multiplex different pads to the same peripheral input, the SIUL provides a register that controls
the selection between the different sources.
Table 37-12. Peripheral input pin selection
PSMI register
SIUL address offset
PSMI[0]
0x500
PSMI[1]
0x501
PSMI[2]
PSMI[3]
PSMI[4]
PSMI[5]
0x502
0x503
0x504
0x505
Peripheral input
CAN0_RXD
CAN1_RXD
DCU_PDI[0]
DCU_PDI[1]
DCU_PDI[2]
DCU_PDI[3]
Mapping of input pin to
peripheral input ¹
0: PCR[17]
1: PCR[109]
0: PCR[26]
1: PCR[83]
2: PCR[111]
0: PCR[17]
1: PCR[109]
0: PCR[16]
1: PCR[110]
0: PCR[26]
1: PCR[111]
0: PCR[27]
1: PCR[112]
37-14
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor