PXD10RM Datasheet, PDF (759/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset: 0x0008
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R_{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
PRI
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1}
Figure 21-3. INTC Current Priority Register (INTC_CPR)
Table 21-4. INTC_CPR Field Descriptions
Field
28–31
PRI[0:3]
Description
Priority. PRI is the priority of the currently executing ISR according to the field values defined in
Table 21-5.
The INTC_CPR masks any peripheral or software settable interrupt request set at the same or lower
priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the
processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector
mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the
value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt
request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the
INTC_CPR’s PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 21.7.5, Priority Ceiling Protocol.”
NOTE
A store to modify the PRI field that closely precedes or follows an access to
a shared resource can result in a non-coherent access to the resource. Refer
to Section 21.7.5.2, Ensuring Coherency” for example code to ensure
coherency.
Table 21-5. PRI Values
PRI
1111
1110
1101
1100
1011
1010
1001
1000
0111
Meaning
Priority 15—highest priority
Priority 14
Priority 13
Priority 12
Priority 11
Priority 10
Priority 9
Priority 8
Priority 7
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-7