PXD10RM Datasheet, PDF (695/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 18-12. Error and Status Register (ESR) field descriptions (continued)
Field
Description
BOFF_INT
ERR_INT
Bus Off’ Interrupt
This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control
Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it
to ‘1’. Writing ‘0’ has no effect.
1 = FlexCAN module entered ‘Bus Off’ state
0 = No such occurrence
Error Interrupt
This bit indicates that at least one of the Error Bits (bits 16-21) is set. If the corresponding mask bit
in the Control Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared
by writing it to ‘1’.Writing ‘0’ has no effect.
1 = Indicates setting of any Error Bit in the Error and Status Register
0 = No such occurrence
Value
00
01
1X
Table 18-13. Fault Confinement State
Meaning
Error Active
Error Passive
Bus Off
18.3.4.9 Interrupt Mask Register High (IMRH)
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (i.e. when the corresponding IFRH bit is set).
Base + 0x0024
0
R _BUF
W ^63M
1
BUF
62M
2
BUF
61M
3
BUF
60M
4
BUF
59M
5
BUF
58M
6
BUF
57M
7
BUF
56M
8
BUF
55M
9
BUF
54M
10
BUF
53M
11
BUF
52M
12
BUF
51M
13
BUF
50M
14
BUF
49M
15
BUF
48M
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R _BUF
W ^47M
17
BUF
46M
18
BUF
45M
19
BUF
44M
20
BUF
43M
21
BUF
42M
22
BUF
41M
23
BUF
40M
24
BUF
39M
25
BUF
38M
26
BUF
37M
27
BUF
36M
28
BUF
35M
29
BUF
34M
30
BUF
33M
31
BUF
32M
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-11. Interrupt Mask Register High (IMRH)
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-25