PXD10RM Datasheet, PDF (243/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

9.4.2.6 eMIOS200 UC B Register (EMIOSB[n])
address: UC[n] base address + 0x04
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
B
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-13. eMIOS200 UC B register (EMIOSB[n])
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address EMIOSB[n].
Both B1 and B2 are cleared by reset. Table 9-13 summarizes the EMIOSB[n] writing and reading accesses
for all operation modes. For more information see section Section 9.5.1.1, UC Modes of Operation.
Depending on the channel configuration it may have EMIOSB register or not. EMIOSB register is required
for the following modes: OPWMB, OPWFMB, MCB. It means that if no mode requiring EMIOSB register
is implemented then the register can be removed during synthesis through proper parameterization.
Table 9-13. EMIOSA[n], EMIOSB[n] and EMIOSALTA[n] Values Assignments
Operation Mode
write
read
Register access
write
read
GPIO
SAIC¹
SAOC¹
MCB¹
A1, A2
A1
B1,B2
B1
-
A2
B2
B2
A2
A1
B2
B2
A2
A1
B2
B2
OPWFMB
A2
A1
B2
B1
OPWMB
A2
A1
B2
B1
1 _{In these modes, the register EMIOSB[n] is not used, but B2 can be accessed.}
alt write
A2
-
-
-
-
-
alt read
A2
-
-
-
-
-
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-17