PXD10RM Datasheet, PDF (267/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

write to A2
cycle n
cycle n+1
clock
prescaler
Selected
counter bus
1
A1 value
A2 value
B1 value
0x000004
0x000008
A1 match
A1 match posedge detection
A1 match negedge detection
4
0x000000
8
1
0x000000
match A1 negedge detection
match A1 posedge detection
8
TIME
B1 match
B1 match negedge detection
output pin
EDPOL = 0
FLAG set event
FLAG pin/register
match B1 negedge detection
Figure 9-35. OPWMB Mode with 0% Duty Cycle
Figure 9-36 describes the operation of the OPWMB mode with the Output Disable signal being asserted.
The Output Disable forces a transition in the output pin to the EDPOL bit value. After deasserted, the
output disable allows the output pin to transition at the following A1 or B1 match. Note that the Output
Disable does not modify the Flag bit behavior. Note that there is one system clock delay between the
assertion of the output disable signal and the transition of the output pin to EDPOL.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-41