PXD10RM Datasheet, PDF (685/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 18-8. Module Configuration Register (MCR) field descriptions (continued)
Field
AEN
IDAM
MAXMB
Description
Abort Enable
This bit is supplied for backwards compatibility reasons. When asserted, it enables the Tx abort
feature. This feature guarantees a safe procedure for aborting a pending transmission, so that no
frame is sent in the CAN bus without notification.
1 = Abort enabled
0 = Abort disabled
ID Acceptance Mode
This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown in
Table 18-9. Note that all elements of the table are configured at the same time by this field (they are
all the same format). See Section 18.3.3, Rx FIFO Structure.
Maximum Number of Message Buffers
This 6-bit field defines the maximum number of message buffers that will take part in the matching
and arbitration processes. The reset value (0x0F) is equivalent to 16 MB configuration. This field
should be changed only while the module is in Freeze Mode.
Maximum MBs in use = MAXMB + 1
Note: MAXMB has to be programmed with a value smaller or equal to the number of available
Message Buffers, otherwise FlexCAN will not transmit or receive frames.
Note: When the Rx FIFO is enabled, it uses 8 MBs. These should be included in the MAXMB total.
Thus, for example, if the Rx FIFO and 4 other MBs are enabled, MAXMB = 11.
IDAM
00
01
10
11
Format
A
B
C
D
Table 18-9. IDAM Coding
Explanation
One full ID (standard or extended) per filter element.
Two full standard IDs or two partial 14-bit extended IDs per filter element.
Four partial 8-bit IDs (standard or extended) per filter element.
All frames rejected.
18.3.4.2 Control Register (CTRL)
This register is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate,
programmable sampling point within an Rx bit, Loop Back Mode, Listen Only Mode, Bus Off recovery
behavior and interrupt enabling (Bus-Off, Error, Warning). It also determines the Division Factor for the
clock prescaler. Most of the fields in this register should only be changed while the module is in Disable
Mode or in Freeze Mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK and
BOFF_REC bits, that can be accessed at any time.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-15