PXD10RM Datasheet, PDF (391/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset: 0x234
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
INP_BUF_p2_hi
W
INP_BUF_p2_lo
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INP_BUF_p1_hi
W
INP_BUF_p1_lo
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Figure 37.
Figure 12-40. Threshold input buffer 1 Register (THRESHOLD_INP_BUF_1)
Table 12-35. THRESHOLD_INP_BUF_1 Field Descriptions
Field
Description
0–7
High Threshold for input buffer for blend stage 2.
INP_BUF_p2_hi
8–15
Low Threshold for input buffer for blend stage 2.
INP_BUF_p2_lo
16–23
High Threshold for input buffer for blend stage 1 (background).
INP_BUF_p1_hi
24–31
Low Threshold for input buffer for blend stage 1 (background plane).
INP_BUF_p1_lo
12.3.4.31 THRESHOLD_INP_BUF_2 Register
Figure 12-41 represents the threshold register for input buffer for plane 3 and plane 4.
Offset: 0x238
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
INP_BUF_p4_hi
W
INP_BUF_p4_lo
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INP_BUF_p3_hi
W
INP_BUF_p3_lo
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Figure 38.
Figure 12-41. THRESHOLD_INP_BUF_2 Register
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
12-59