PXD10RM Datasheet, PDF (246/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 9-14. EMIOSC[n] Field Descriptions (continued)
Field
Description
bit 7
DMA
bit 9:12
IF[0:3]
bit 13
FCK
bit 14
FEN
bit 18
FORCMA
bit 19
FORCMB
bit 21:22
BSL[0:1]
bit 23
EDSEL
Direct Memory Access bit
The DMA bit selects if the FLAG generation will be used as an interrupt or as a DMA request.
1 = Flag/overrun assigned to DMA request
0 = Flag/overrun assigned to Interrupt request
Input Filter bits
The IF[0:3] bits control the programmable input filter, selecting the minimum input pulse width that
can pass through the filter, as shown in Table 9-17. For output modes, these bits have no meaning.
Filter Clock select bit
The FCK bit selects the clock source for the programmable input filter.
1 = main clock
0 = prescaled clock
FLAG Enable bit
The FEN bit allows the Unified Channel FLAG bit to generate an interrupt signal or a DMA request
signal (The type of signal to be generated is defined by the DMA bit).
1 = Enable (FlAG will generate an interrupt or DMA request)
0 = Disable (FLAG does not generate an interrupt or DMA request)
Force Match A bit
For output modes, the FORCMA bit is equivalent to a successful comparison on comparator A
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit
is valid for every output operation mode which uses comparator A, otherwise it has no effect.
1 = Force a match at comparator A
0 = Has no effect
Note: For input modes, the FORCMA bit is not used and writing to it has no effect.
Force Match B bit
For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit
is valid for every output operation mode which uses comparator B, otherwise it has no effect.
1 = Force a match at comparator B
0 = Has not effect
Note: For input modes, the FORCMB bit is not used and writing to it has no effect.
Bus Select bits
The BSL[0:1] bits are used to select either one of the counter buses or the internal counter to be used
by the Unified Channel. Refer to Table 9-18 for details.
Edge Selection bit
For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a
pulse or just by a single edge as defined by the EDPOL bit. When not shown in the mode of operation
description, this bit has no effect.
1 = Both edges triggering
0 = Single edge triggering defined by the EDPOL bit
For GPIO in mode, the EDSEL bit selects if a FLAG can be generated.
1 = No FLAG is generated
0 = A FLAG is generated as defined by the EDPOL bit
For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.
1 = The output flip-flop is toggled
0 = The EDPOL value is transferred to the output flip-flop
9-20
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor