PXD10RM Datasheet, PDF (734/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

20.4.3.1 I²C Bus Address Register
This register contains the address the I²C Bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Offset 0x00000
Access: Read/write any time
0
1
2
3
4
5
6
7
R
0
ADR
W
Reset
0
0
0
0
0
0
0
0
Figure 20-3. I²C Bus Address Register (IBAD)
Table 20-2. IBAD Field Descriptions
Field
Description
ADR Slave Address. Specific slave address to be used by the I²C Bus module.
Note: The default mode of I²C Bus is slave mode for an address match on the bus.
20.4.3.2 I²C Bus Frequency Divider Register
Offset 0x0001
Access: Read/write any time
0
1
2
3
4
5
6
7
R
IBC
W
Reset
0
0
0
0
0
0
0
0
Figure 20-4. I²C Bus Frequency Divider Register (IBFD)
Table 20-3. IBFD Field Descriptions
Field
Description
IBC I-Bus Clock Rate. This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider. The IBC bits are decoded to give the Tap and Prescale values as
follows:
0–1 select the prescaled shift register (see Table 20-4)
2–4 select the prescaler divider (see Table 20-5)
5–7 select the shift register tap point (see Table 20-6)
IBC[0:1]
00
01
10
11
Table 20-4. I-Bus Multiplier Factor
MUL
01
02
04
RESERVED
20-4
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor