PXD10RM Datasheet, PDF (358/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Offset:
0x00C (CtrlDescL0_4)
0x028 (CtrlDescL1_4)
0x044 (CtrlDescL2_4)
0x060 (CtrlDescL3_4)
0x07C (CtrlDescL4_4)
0x098 (CtrlDescL5_4)
0x0B4 (CtrlDescL6_4)
0x0D0 (CtrlDescL7_4)
0x0EC (CtrlDescL8_4)
0x108 (CtrlDescL9_4)
0x124 (CtrlDescL10_4)
0x140 (CtrlDescL11_4)
0x15C (CtrlDescL12_4)
0x178 (CtrlDescL13_4)
0x190 (CtrlDescL14_4)
0x1B0 (CtrlDescL15_4)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
W
EN
TILE
_EN
DAT
A_S
EL
SAF
ETY
_EN
TRANS
BPP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
W
LUOFFS
0
BB
AB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 4.
Figure 12-7. CtrlDescL0_4 Register
Table 12-9. CtrlDescL0_4 Field Descriptions
Field
0
EN
1
TILE_EN
2
DATA_SEL
3
SAFETY_EN
Description
Enable the layer
1’b1: ON
1’b0: OFF
Enable the Tile Mode
1’b1: ON
1’b0: OFF
Selects the Tile data either from MCU memory or CLUT
1’b0: Tile Mode data resides in the MCU memory
1’b1: Tile mode data resides in the CLUT
Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this
should be set to 0.
1’b1: Safety Mode is enabled for this layer
1’b0: Safety Mode is disabled
12-26
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor