PXD10RM Datasheet, PDF (203/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

8.5.1 Main features
• External crystal oscillator (FXOSC) digital interface
• Oscillator clock available interrupt
• Oscillator bypass mode
• Output clock division factors ranging from 1,2,3....32
8.5.2 Functional Description
The crystal oscillator circuit includes an internal oscillator driver and an external crystal circuitry. It
provides an output clock that can be provided to PLL or used as a reference clock to specific modules
depending on system needs.
The crystal oscillator is controlled by the MC_ME module. The OSCON bit of ME_XXX_MCR registers
controls the powerdown of oscillator based on the current device mode while S_OSC of ME_GS register
provides the oscillator clock available status.
After system reset, the oscillator is put to power down state and software has to switch on when required.
Whenever the crystal oscillator is switched on from off state, OSCCNT counter starts and when it reaches
the value EOCV[7:0]*512, oscillator clock is made available to the system. Also an interrupt pending bit
I_OSC of OSC_CTL register is set. An interrupt will be generated if the interrupt mask bit M_OSC is set.
The oscillator circuit can be bypassed by setting OSC_CTL[OSCBYP]. This bit can only be set by the
software. System reset is needed to reset this bit. In this bypass mode, the output clock has the same
polarity as external clock applied on EXTAL pin and the oscillator status is forced to ‘1’. The bypass
configuration is independent of the powerdown mode of the oscillator.
Table 8-14 shows the truth table of different configurations of oscillator.
Table 8-14. Truth table of crystal oscillator
ENABLE
0
x
1
BYP
0
1
0
XTAL
EXTAL CK_OSCM
OSC MODE
No crystal,
Hiz
x
Crystal
Gnd
No crystal,
Hiz
Ext clock
Crystal
Ext clock
0
EXTAL
EXTAL
EXTAL
Power down, IDDQ
Bypass, OSC Disabled
Normal, OSC Enabled
Normal, OSC Enabled
The crystal oscillator clock can be further divided by a configurable factor in the range 1 to 32 to generate
the divided clock to match system requirements. This division factor is specified by the OSCDIV[4:0] bits
of OSC_CTL register.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-25