PXD10RM Datasheet, PDF (596/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

5. Write a logic 1 to the UT0.AIE bit to start the ECC Logic Check.
6. Wait until the UT0.AID bit goes high.
7. Compare UMISR0-4 content with the expected result.
8. Write a logic 0 to the UT0.AIE bit.
Notice that when UT0.AID is low UMISR0-4, UT1-2 and bits MRE, MRV, EIE, AIS and DSI7-0 of UT0
are not accessible: reading returns undeterminate data and write has no effect.
Example 17-7. ECC logic check
UT0
= 0xF9F99999;
UT1
= 0x55555555;
UT2
= 0xAAAAAAAA;
UT0
= 0x80FF0000;
UT0
= 0x80FF0008;
UT0
= 0x80FF000A;
do
{ tmp
= UT0;
} while ( !(tmp & 0x00000001) );
data0
= UMISR0;
data1
= UMISR1;
data2
= UMISR2;
data3
= UMISR3;
data4
= UMISR4;
UT0
= 0x00000000;
/* Set UTE in UT0: Enable User Test */
/* Set DAI31-0 in UT1: Even Word Input Data */
/* Set DAI63-32 in UT2: Odd Word Input Data */
/* Set DSI7-0 in UT0: Syndrome Input Data */
/* Set EIE in UT0: Select ECC Logic Check */
/* Set AIE in UT0: Operation Start */
/* Loop to wait for AID=1 */
/* Read UT0 */
/* Read UMISR0 content (expected 0x55555555) */
/* Read UMISR1 content (expected 0xAAAAAAAA) */
/* Read UMISR2 content (expected 0x55555555) */
/* Read UMISR3 content (expected 0xAAAAAAAA) */
/* Read UMISR4 content (expected 0x00FF00FF) */
/* Reset UTE, AIE and EIE in UT0: Operation End */
17.2.7.2 Error Correction Code
The Flash Macrocell provides a method to improve the reliability of the data stored in Flash: the usage of
an Error Correction Code. The word size is fixed of 64 bits.
At each Double Word of 64 bits there are associated 8 ECC bits that are programmed in such a way to
guarantee a Single Error Correction and a Double Error Detection (SEC-DED).
17.2.7.2.1 ECC Algorithms
The Flash Macrocell supports one ECC Algorithm: “All ‘1’s No Error”. A modified Hamming code is used
that ensures the all erased state (i.e. 0xFFFF.....FFFF) data is a valid state, and will not cause an ECC error.
This allows the user to perform a blank check after a sector erase operation.
17.2.7.3 Protection Strategy
Two kind of protections are available: Modify Protection to avoid unwanted program/erase in Flash sectors
and Censored Mode to avoid piracy.
17.2.7.3.1 Modify Protection
The Flash Modify Protection information is stored in non-volatile Flash cells located in the Test Flash. This
information is read once during the Flash initialization phase following the exit from Reset and is stored
in volatile registers that act as actuators.
The reset state of all the Volatile Modify Protection Registers is the protected state.
17-46
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor