PXD10RM Datasheet, PDF (409/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

12.4.4 Proper sequence for enabling and disabling the DCU
It is important to follow a correct sequence when enabling and disabling the DCU.
To enable the panel it is possible to set DCU_MODE to be active and then set RASTER_EN. It is possible
to set RASTER_EN and then set DCU_MODE to be active. It is also possible to set both in the same write.
It is not possible to set DCU_MODE to be active and then set it to 0 before the RASTER_EN bit has been
set.
To disable the panel MCU_MODE must be set to 0 in the same write as or before RASTER_EN can be set
to 0.
It is not possible to set RASTER_EN to 0 (disable raster) before disabling the pixel clock.
12.4.5 Layer configuration and blending
Users control the graphical content of the TFT panel by manipulating the configuration of elements in the
DCU called layers. Each layer has a control descriptor that defines the size, position, memory encoding,
blending, and memory location of the graphic to be displayed. The DCU provides 16 independent layers
that are identical except that they have a fixed priority with respect to each other, and this affects how
individual pixels are blended when layers overlap. The blending setting on each layer allows the pixels on
that layer to be opaque, partially transparent, or fully transparent, which allows them to combine with
pixels on other layers that they overlap.
12.4.5.1 Blending priority of layers
The 16 layers available in the DCU are each fixed in priority order, with layer 0 being the highest priority,
layer 1 being the second highest priority, and so on until layer 15, which is the lowest priority. The priority
is used by the DCU to define how to blend individual pixels within the layers. For example, if layer 0 is
defined as not being blended with other layers and a pixel on layer 0 overlaps a pixel on layer 1 then the
pixel on layer 0 will be visible on the panel unchanged by the pixel on layer 1. However, if layer 0 is
defined as being partially transparent, then the DCU will blend the overlapping pixel such that the result
is a combination of the pixel on layer 0 and the pixel on layer 1. It is possible to blend up to four layers at
each pixel position.
As there is a maximum number of layers that can blended together, then any pixel on a layer that is lower
than the threshold priority will not be included in any blend. If a pixel is on a layer that has the lowest
priority in any blending scheme, then the blending settings for that pixel are ignored and the pixel is treated
as a background pixel. This means that a lower priority layer may have some pixels completely obscured
by those on higher priority layers on one part of the panel, and some other pixels visible or blended on
other parts of the panel.
Figure 12-58 shows how the pixel blend takes place inside the DCU. The priority of the layers determines
at which stage of the blend the pixel enters. Any pixels lower than the threshold priority are ignored and,
as can be seen, the blend settings for the lowest priority pixel is also ignored. The maximum number of
pixels in the blend is configured by the BLEND_ITER bit field in the DCU_MODE register. As can be
seen in the figure, the blending process is iterative so that four-pixel blending takes more DCU clock cycles
than three-pixel blending, and three-pixel blending takes more DCU clock cycles than two-pixel blending.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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