PXD10RM Datasheet, PDF (638/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

p0
AHB port 0
p1
AHB port 1
b0, bk0
flash memory bank0
b1, bk1
flash memory bank1 (optional)
b2, bk2
flash memory bank2
b02
flash memory banks 0 and 2
Finally since the page buffers and temporary holding registers are associated with both an AHB input port
and a flash bank, they use a bx_py nomenclature. For example, the b0_p0 page buffer refers to the bank0,
port 0 storage elements.
17.4.1.1 Overview
The PFLASH2P_LCA supports a 32-bit data bus width at the two AHB ports and connections to 128-bit
read data interfaces from three memory banks, where each bank contains one (or more) instantiations of
the low-cost flash memory array. Typically, flash bank0 is connected to the first code flash memory, bank2
is connected to a second code flash memory, and bank1 is connected to the optional data flash memory.
The memory controller capabilities vary between the banks with each bank’s functionality optimized for
the typical use cases associated with the attached flash memory. As an example, the PFLASH2P_LCA
logic associated with bank0 contains 2 four-entry “page” buffers, one for each AHB input port, where each
buffer entry contains 128 bits of data (1 flash page) plus an associated controller which prefetches
sequential lines of data from the flash array into the buffer. This structure is repeated for bank2, providing
a total of four copies of the 4-entry page buffer. The controller logic associated with bank1 is simpler and
only supports two 128-bit registers (again, one for each AHB port) which serve as temporary page holding
registers and no support of any prefetching. Prefetch buffer hits from any of the page buffers or temporary
holding registers support zero-wait AHB data phase responses. AHB read requests which miss the buffers
generate the needed flash array access and the read data is forwarded to the AHB port upon completion,
typically incurring two wait-states at an operating frequency of 60 - 64 MHz. The logic of the
PFLASH2P_LCA is structured to support simultaneous AHB accesses from the two ports fully in parallel
when the references are targeted to different memory banks. If simultaneous AHB accesses reference the
same bank, then arbitration logic within the PFLASH2P_LCA determines the order the references are
granted access to the bank.
This memory controller is optimized for applications where a cacheless processor core, such as the
e200z0h, is connected through the platform to on-chip memories, e.g., flash and RAM, where the
processor and platform operate at the same frequency. For these applications, the 2-stage pipeline
AMBA-AHB system bus is effectively mapped directly into stages of the processor’s pipeline and zero
wait-state responses for most memory accesses are critical for providing the required level of system
performance.
17.4.1.2 Features
The following list summarizes the key features of the PFLASH2P_LCA:
• Triple bank interfaces support up to a total of 16 Mbytes of flash memory, partitioned as two 4
Mbyte code banks (0, 2) and a separate optional 8 Mbyte data bank (1)
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor