PXD10RM Datasheet, PDF (1191/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

VDDM
T1
T3
VDDM
T5
T7
COSP
T2
COSM
T4
SINP
T6
SINM
T8
VSSM
VSSM
Figure 36-16. Current flow for Integration (STEP = 2, ITGDCL = 1)
Figure 36-17 below shows that the sine coil is driven for STEP = 3 in reverse direction with respect to
STEP = 1 (M -> P direction). Again the other coil (cosine) is isolated from the analog supply voltages
because it is the integration phase of the current BIS.
VDDM
VDDM
T1
T3
T5
T7
COSP
T2
COSM
T4
SINP
T6
SINM
T8
VSSM
VSSM
Figure 36-17. Current flow for Integration (STEP = 3, ITGDCL = 1)
36.6.2 Setting of the PRESCALE Register
36.6.2.1 Timing Resolution Considerations
Set the ACDIV bits to the lowest division factor possible, resulting in the highest possible clock frequency
for the integration accumulator. This will give the most precise result.
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
36-25