PXD10RM Datasheet, PDF (756/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

21.4.1.1 Software Vector Mode
In software vector mode, the interrupt exception handler software must read a register in the INTC to
obtain the vector associated with the interrupt request to the processor. The INTC will use software vector
mode for a given processor when its associated HVEN bit in INTC_MCR is negated. The hardware vector
enable signal to processor 0 or processor 1 is driven as negated when its associated HVEN bit is negated.
The vector is read from INC_IACKR. Reading the INTC_IACKR negates the interrupt request to the
associated processor. Even if a higher priority interrupt request arrived while waiting for this interrupt
acknowledge, the interrupt request to the processor will negate for at least one clock. The reading also
pushes the PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated
INTC_CPR with the new priority.
Furthermore, the interrupt vector to the processor is driven as all 0s. The interrupt acknowledge signal
from the associated processor is ignored.
21.4.1.2 Hardware Vector Mode
In hardware vector mode, the hardware signals the interrupt vector from the INTC in conjunction with a
processor that can use that vector. This hardware causes the first instruction to be executed in handling the
interrupt request to the processor to be specific to that vector. Therefore, the interrupt exception handler is
specific to a peripheral or software configurable interrupt request rather than being common to all of them.
The INTC uses hardware vector mode for a given processor when the associated HVEN bit in the
INTC_MCR is asserted. The hardware vector enable signal to the associated processor is driven as
asserted. When the interrupt request to the associated processor asserts, the interrupt vector signal is
updated. The value of that interrupt vector is the unique vector associated with the preempting peripheral
or software configurable interrupt request. The vector value matches the value of the INTVEC field in the
INTC_IACKR field in the INTC_IACKR, depending on which processor was assigned to handle a given
interrupt source.
The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt
acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for the
interrupt acknowledge, the interrupt request to the processor will negate for at least one clock.
The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in
the associated INTC_CPR register onto the associated LIFO and updates the associated PRI in the
associated INTC_CPR register with the new priority. This pushing of the PRI value onto the associated
LIFO and updating PRI in the associated INTC_CPR does not occur when the associated interrupt
acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI
value in the associated INTC_CPR register would need to be pushed and the previously last pushed PRI
value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR is updated
with the new priority, and the associated LIFO is neither pushed or popped.
21.4.1.3 Debug Mode
The INTC operation in debug mode is identical to its operation in normal mode.
21-4
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor