PXD10RM Datasheet, PDF (1172/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

36.3.3.1 SSD Control and Status Register (CONTROL)
Figure 36-3 below describes the fields of the main control (CONTROL) register:
Offse 0x00
t
Access: User read/write
15 14 13
R0
STEP
W TRIG
Reset 0 0 0
12
RCIR
0
11
10
9
87
6
5
432
1
0
0 BLNST ITGST 0 0 0
ITGDIR BLNDCL ITGDCL RTZE
SDCPU DZDIS
0
0
0
00 0
0
000
0
0
Figure 36-3. SSD Control and Status Register (CONTROL)
The function of the CONTROL register bits is shown in Table 36-4.
Table 36-4. CONTROL Register Field Description
Field
Description
15 TRIG - Trigger Blanking -> Integration sequence (BIS).
1 Sequence of blanking -> integration is triggered.
0 No effect.
14-13
STEP - Full Step State. These bits determine which coil is driven for SM movement,. Refer to Table 36-11
for details of the step states.
00 Select0^ angle (east pole) state for the electromagnetic field in the SM.
01 Select90^ angle (north pole) state for the electromagnetic field in the SM.
10 Select180^ angle (west pole) state for the electromagnetic field in the SM.
11 Select270^ angle (south pole) state for the electromagnetic field in the SM.
12 RCIR - Blanking Polarity for coil recirculation. Refer to Section 36.4, Functional Description,” for details of
the recirculation mode.
1 Coil recirculation via low side transistors (VSSM, analog GND).
0 Coil recirculation via high side transistors (VDDM, analog supply voltage).
11 ITGDIR - Direction (polarity) of integration. Refer to Section 36.4.1.4.3, DC Offset Cancellation” for details
10 BLNDCL - Drive Coil during Blanking.
1 During the BIS blanking phase the other coil is actually driven by the SSD block (genuine use case).
0 During the BIS blanking phase the other coils is not driven by the SSD. The SM will not move during
blanking.
9 ITGDCL - Drive Coil during Integration and outside of any BIS.
1 During the BIS integration phase and outside of any BIS the other coil is actually driven by the SSD
block (genuine use case). Outside of any BIS the same coil is driven.
0 During the BIS integration phase the other coils is not driven by the SSD. Outside of any BIS no coil is
driven. The SM will not move during integration (not useful for SSD).
8 RTZE - Return to Zero Enable. This is in fact the enable bit of the SSD logic to take over control of the SM
coils¹.
1 Control of the SM coils by the SSD block is enabled.
0 Control of the SM coils by the SSD block is disabled.
6 BLNST - Blanking Status. Refer to Section 36.1.3.2, Normal Mode” for details.
1 The SSD block is currently in the blanking phase of an ongoing BIS.
0 The SSD block is not in the blanking phase of an ongoing BIS.
36-6
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor