PXD10RM Datasheet, PDF (258/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

The internal counter values operates within a range from 0x1 up to register A1 value. If when entering
MCB mode coming out from GPIO mode the internal counter value is not within that range then the A
match will not occur causing the channel internal counter to wrap at the maximum counter value which is
0xFFFF for a 16-bit counter. After the counter wrap occurs it returns to 0x1 and resume normal MCB mode
operation. Thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to A1
register value range when the MCB mode is entered.
MODE[6] bit selects internal clock source if cleared or external if set. When external clock is selected the
input channel pin is used as the channel clock source. The active edge of this clock is defined by EDPOL
and EDSEL bits in the EMIOSC[n] channel register.
When entering in MCB mode, if up counter is selected by MODE[4]=0 (MODE[0:6]=101000b), the
internal counter starts counting from its current value to up direction until A1 match occurs. The internal
counter is set to 0x1 when its value matches A1 value and a clock tick occurs (either prescaled clock or
input pin event).
If up/down counter is selected by setting MODE[4]=1, the counter changes direction at A1 match and
counts down until it reaches the value 0x1. After it has reached 0x1 it is set to count in up direction again.
B1 register is used to generate a match in order to set the internal counter in up-count direction if up/down
mode is selected. Register B1 cannot be changed while this mode is selected.
Note that the MCB mode counts between 0x1 and A1 register value. Only values greater than 0x1 must be
written at A1 register. Loading values other than those leads to unpredictable results. The counter cycle
period is equal to A1 value in up counter mode. If in up/down counter mode the period is defined by the
expression: (2*A1)-2.
Figure 9-25 describes the counter cycle for several A1 values. Register A1 is loaded with A2 register value
at the cycle boundary. Thus any value written to A2 register within cycle n will be updated to A1 at the
next cycle boundary and therefore will be used on cycle n+1. The cycle boundary between cycle n and
cycle n+1 is defined as when the internal counter transitions from A1 value in cycle n to 0x1 in cycle n+1.
Note that the FLAG is generated at the cycle boundary and has a synchronous operation, meaning that it
is asserted one system clock cycle after the FLAG set event.
9-32
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor