PXD10RM Datasheet, PDF (671/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Chapter 18
FlexCAN
18.1 Introduction
The FlexCAN module is a communication controller implementing the CAN protocol according to the
CAN 2.0B protocol specification. A general block diagram is shown in Figure 18-1, which describes the
main sub-blocks implemented in the FlexCAN module, including two embedded memories, one for
storing Message Buffers (MB) and another one for storing Rx Individual Mask Registers. Support for up
to 64 Message Buffers is provided. The functions of the sub-modules are described in subsequent sections.
MB63
RXIMR63
RXIMR62
MB62
ID Mask
Storage
64/128/256-
byte RAM
Message
Buffer
Storage
288/544/1056-
byte RAM
Message
Buffer
Management
max MB #
(0–63)
CAN
Protocol
Interface
CAN Tx
CAN Rx
RXIMR1
RXIMR0
MB1
MB0
Bus Interface Unit
IP Bus Interface
Clocks, Address & Data buses,
Interrupt and Test Signals
Figure 18-1. FlexCAN block diagram
18.1.1 Overview
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting
the specific requirements of this field: real-time processing, reliable operation in the EMI environment of
a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the
CAN protocol specification, Version 2.0 B [Ref. 1], which supports both standard and extended message
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-1