PXD10RM Datasheet, PDF (656/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

and buffer enables are defined on a per AHB port in the PFCR0 and PFCR1 registers. Refer to
Section 17.4.3.2, Register Descriptions” for a description of these control fields.
17.4.4.8.1 Inst/Data Prefetch Triggering
Prefetch triggering may be enabled for instruction reads via the Bx_Py_IPFE control field, while
prefetching for data reads is enabled via the Bx_Py_DPFE control field. Additionally, the Bx_Py_PFLIM
field must also be set to enable prefetching. Prefetches are never triggered by write cycles.
17.4.4.8.2 Per-Master Prefetch Triggering
Prefetch triggering may be also controlled for individual bus masters. AHB accesses indicate the
requesting master via the hmaster[3:0] inputs. Refer to PFAPR description for details on these controls.
17.4.4.8.3 Buffer Allocation
Allocation of the page read buffers is controlled via page buffer configuration (Bx_Py_BCFG) field. This
field defines the operating organization of the four page buffers. The buffers can be organized as a “pool”
of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated
to instruction or data accesses. For the fixed partition, two configurations are supported. In one
configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. In
the second configuration, buffers 0, 1 and 2 are allocated for instruction fetches and buffer 3 reserved for
data accesses.
17.4.4.8.4 Buffer Invalidation
The page read buffers may be invalidated under hardware or software control.
Any falling edge transition of the array’s bkn_fl_done signal causes the page read buffers to be marked as
invalid. This input is negated by the flash array at the beginning of all program/erase operations as well as
in certain other cases. Buffer invalidation occurs at the next AHB non-sequential access boundary, but does
not affect a burst from a page read buffer which is in progress.
Software may invalidate the buffers by clearing the Bx_Py_BFE bit, which also disables the buffers.
Software may then re-assert the Bx_Py_BFE bit to its previous state, and the buffers will have been
invalidated.
One special case needing software invalidation relates to page buffer “hits” on flash data which was tagged
with a single-bit ECC event on the original array access. Recall that the page buffer structure includes an
status bit signaling the array access detected and corrected a single-bit ECC error. On all subsequent buffer
hits to this type of page data, a single-bit ECC event is signaled by the PFLASH2P_LCA. Depending on
the specific hardware configuration, this reporting of a single-bit ECC event may generate an ECC alert
interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by
software after the first notification of the single-bit ECC event.
Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on
haddr[28:24] to support wait-state emulation.
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PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor