PXD10RM Datasheet, PDF (901/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

Table 24-9. MPU_RGDAACn Field Descriptions (continued)
Field
Description
21–22
M1SM
23–25
M1UM
26
M0PE
27–28
M0SM
29–31
M0UM
Bus master 1 supervisor mode access control. This 2-bit field defines the access controls for bus master
1 when operating in supervisor mode. The M1SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M1UM for user mode
Bus master 1 user mode access control. This 3-bit field defines the access controls for bus master 1
when operating in user mode. The M1UM field consists of three independent bits, enabling read, write
and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an
attempted access of that mode may be terminated with an access error (if not allowed by any other
descriptor) and the access not performed.
Bus master 0 process identifier enable. If set, this flag specifies that the process identifier and mask
(defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region
hit evaluation does not include the process identifier.
Bus master 0 supervisor mode access control. This 2-bit field defines the access controls for bus master
0 when operating in supervisor mode. The M0SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M0UM for user mode
Bus master 0 user mode access control. This 3-bit field defines the access controls for bus master 0
when operating in user mode. The M0UM field consists of three independent bits, enabling read, write
and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an
attempted access of that mode may be terminated with an access error (if not allowed by any other
descriptor) and the access not performed.
24.3 Functional description
In this section, the functional operation of the MPU is detailed. In particular, subsequent sections discuss
the operation of the access evaluation macro as well as the handling of error-terminated AHB bus cycles.
24.3.1 Access evaluation macro
As previously discussed, the basic operation of the MPU is performed in the access evaluation macro, a
hardware structure replicated in the two-dimensional connection matrix. As shown in Figure 24-10, the
access evaluation macro inputs the AHB system bus address phase signals (AHB_ap) and the contents of
a region descriptor (RGDn) and performs two major functions: region hit determination (hit_b) and
detection of an access protection violation (error).
Freescale Semiconductor
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
24-15