PXD10RM Datasheet, PDF (1024/1332 Pages) Freescale Semiconductor, Inc – PXD10 Microcontroller

30.4.3.5 SPI Status Register (QSPI_SPISR)
The QSPI_SPISR contains status and flag bits. The bits reflect the status of the QuadSPI and indicate the
occurrence of events that can generate interrupt or DMA requests. Software can clear flag bits in the
QSPI_SPISR by writing a ‘1’ to it. Writing a ‘0’ to a flag bit has no effect. This register may not be writable
in MDIS Mode due to the use of power saving mechanisms.
Address: QSPI_BASE + 0x02C
Write: Enabled Mode
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R¹ _TCF
TXR
XS
0
EOQ TFU
FF
0 TFFF 0
0
0
0
0
RFO
F
0
RFD
F
0
W w1c
w1c w1c
w1c
w1c
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27
R¹
TXCTR
TXNXTPTR
RXCTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-5. SPI Status Register (QSPI_SPISR)
1_{When in SFM Mode all 0’s are read.}
28 29 30 31
POPNXTPTR
0000
Table 30-18. QSPI_SPISR Field Descriptions
Field
TCF
TXRXS
EOQF
TFUF
Description
Transfer Complete Flag. The TCF bit indicates that all bits in a frame have been shifted out. The TCF
bit is set at the end of the frame transfer. The TCF bit remains set until cleared by software.
0 Transfer not complete
1 Transfer complete
TX & RX Status. The TXRXS bit reflects the status of the QuadSPI. See Section 30.5.2.1, Start and
Stop of SPI Transfers” for information on how what causes this bit to be negated or asserted.
0 TX and RX operations are disabled (QuadSPI is in STOPPED state)
1 TX and RX operations are enabled (QuadSPI is in RUNNING state)
End of Queue Flag. The EOQF bit indicates that transmission in progress is the last entry in a queue.
The EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end
of the transfer is reached. The EOQF bit remains set until cleared by software. When the EOQF bit
is set, the TXRXS bit is automatically cleared.
0 EOQ is not set in the executing command
1 EOQ bit is set in the executing SPI Command
TX FIFO Underrun Flag. The TFUF bit indicates that an underrun condition in the TX FIFO has
occurred. The transmit underrun condition is detected only in SPI Slave Mode. The TFUF bit is set
when the TX FIFO of a QuadSPI operating in SPI slave mode is empty, and a transfer is initiated by
an external SPI master. The TFUF bit remains set until cleared by software.
0 TX FIFO underrun has not occurred
1 TX FIFO underrun has occurred
30-20
PXD10 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor