SH7720 Datasheet, PDF (998/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 27 A/D Converter
27.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has three
operating modes: single mode, multi mode, and scan mode.
27.4.1 Single Mode
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit in the A/D control/status register (ADCSR) is set to 1 by
software. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0
when conversion ends.
When conversion ends the ADF bit in ADCSR is set to 1. If the ADIE bit in ADCSR is also set to
1 and DMASL is cleared to 0, an ADI interrupt is requested at this time. To clear the ADF flag to
0, first read ADF, then write 0 to ADF.
When the mode or analog input channel must be switched during A/D conversion, to prevent
incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the
necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set
at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 27.2 shows a timing diagram for this example.
1. Start the clock supply to the ADC module (clear the MSTP33 bit in STBCR3 to 0) to run the
ADC module.
2. Single mode is selected (MULTI = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 =
1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
3. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
4. When ADF = 1, ADIE = 1, and DMASL = 0, an ADI interrupt is requested.
5. The A/D interrupt handling routine starts.
6. The routine reads ADF, then writes 0 to the ADF flag.
7. The routine reads and processes the conversion result (ADDRB = 0).
8. Execution of the A/D interrupt handling routine ends.
9. Stop the clock supply to the ADC module (set the MSTP33 bit in STBCR3 to 1) to place the
ADC in the module standby state.
Rev. 3.00 Jan. 18, 2008 Page 936 of 1458
REJ09B0033-0300