SH7720 Datasheet, PDF (922/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
(2) Transmit Data Register
The transmit data register must not write data which is more than maximum packet size. In case of
the transmit data register which has the dual FIFO buffer, the maximum number of data which can
be written in a single time is maximum packet size. Write 1 to TRG/PKTE after data is written.
This writing switches the FIFO buffer. Then, the next data can be written to another buffer.
Therefore data must not be written in both buffers in a single time.
25.9.4 Assigning EP0 Interrupt Sources
The EP0 interrupt sources assigned to IFR0 (bits 0, 1, and 2) must be assigned to the same
interrupt pins by ISR0. The other interrupt sources have no restrictions.
25.9.5 FIFO Clear when DMA Transfer is Set
When the DMA transfer is enabled in endpoint 1, the data register cannot be cleared. Cancel the
DMA transfer before clearing the data register.
25.9.6 Note on Using TR Interrupt
The bulk-in transfer has a transfer request interrupt (TR interrupt). The following points should be
noted when using a TR interrupt.
When the IN token is sent from the USB host and there is no data in the corresponding EP FIFO,
the TR interrupt flag is set. However, the TR interrupt is generated continuously at the timing as
shown in figure 20.18. In this case, note that erroneous operation should not occur.
Note:
When the IN token is received and there is no data in the corresponding EP FIFO, an NAK
is determined. However, the TR interrupt flag is set after an NAK handshake is
transmitted. Therefore when the next IN token is received before TRG/PKTE is written,
the TR interrupt flag is set again.
Rev. 3.00 Jan. 18, 2008 Page 860 of 1458
REJ09B0033-0300