SH7720 Datasheet, PDF (492/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
CHCR
RS[3:0]
1000
1110
DMARS ^{DMA Transfer}
Request
DMA Transfer
MID
RID Source
Request Signal
Source
100000 11 USBF
transmitter
Transmit data empty request Any
00 USBF receiver Transmit data full request EPDR1
101000 01
10
SIM
transmitter
SIM receiver
TXI (transmit data empty)
RXI (receive data full)
Any
SCRDR
101010 00
MMC
transmitter
Receive data empty request Any
MMC receiver Receive data full request Data register
101100 01
10
101101 01
10
110000 01
SIOF0
TXI0 (transmit FIFO data Any
transmitter empty)
SIOF0
receiver
RXI0 (receive FIFO data full) SIRDR0
SIOF1
TXI1 (transmit FIFO data Any
transmitter empty)
SIOF1
receiver
RXI1 (receive FIFO data full) SIRDR0
SD transmitter Transmit data empty request Any
10 SD receiver Receive data full request Data register

 ADC
ADI (A/D conversion end) ADDR
Bus
Destination Mode
EPDR2
Cycle
steal
Any
Cycle
steal
SCTDR
Cycle
steal
Any
Cycle
steal
Data register Cycle
steal
Any
Cycle
steal
SITDR0
Cycle
steal
Any
Cycle
steal
SITDR1
Cycle
steal
Any
Cycle
steal
Data register Cycle
steal
Any
Cycle
steal
Any
Cycle
steal
Rev. 3.00 Jan. 18, 2008 Page 430 of 1458
REJ09B0033-0300