SH7720 Datasheet, PDF (1036/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 29 PC Card Controller (PCC)
Bit
Bit Name Initial Value R/W Description
3
P0CDE 0
R/W PCC0 Card Detect Change Enable
Bit 3 enables or disables the interrupt request when the
values of the CD1 and CD2 are changed.
0: No interrupt occurs for the PC card connected to
area 6 regardless of the values of the CD1 and CD2
1: An interrupt occurs for the PC card connected to
area 6 when the values of the CD1 and CD2 are
changed
2
P0RE
0
R/W PCC0 Ready Change Enable
When the PC card connected to area 6 is on the IC
memory card interface, bit 2 enables or disables the
interrupt request when the value of the RDY/BSY is
changed. This bit has no meaning on the I/O card
interface.
0: No interrupt occurs for the PC card connected to
area 6 regardless of the value of the RDY/BSY
1: An interrupt occurs for the PC card connected to
area 6 when the value of the RDY/BSY is changed
from 0 to 1
1
P0BWE 0
R/W PCC0 Battery Warning Enable
When the PC card connected to area 6 is on the IC
memory card interface, bit 1 enables or disables the
interrupt request when the BVD2 or BVD1 are in the
state in which "the battery must be changed although
the data is guaranteed". This bit has no meaning on the
I/O card interface.
0: No interrupt occurs when the BVD2 or BVD1 are in
the state in which "the battery must be changed
although the data is guaranteed"
1: An interrupt occurs when the BVD2 or BVD1 are in
the state in which "the battery must be changed
although the data is guaranteed"
Rev. 3.00 Jan. 18, 2008 Page 974 of 1458
REJ09B0033-0300