SH7720 Datasheet, PDF (470/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 shows the block diagram of the DMAC.
On-chip
memory
On-chip peripheral
module
DMA transfer
request signal
DMA transfer acknowledge signal
Interrupt controller
DEIn
Iteration
control
Register
control
Start-up
control
Request
priority
control
DMAC module
SARn
DARn
DMATCRn
CHCRn
DMAOR
DMARS0 to
DMARS2
External
ROM
External
RAM
External
I/O (memory
mapped)
External
I/O (with
acknowledge-
ment)
DACK0, DACK1
TEND0, TEND1
DREQ0, DREQ1
Bus
interface
Bus state
controller
[Legend]
SARn:
DMA source address register
DARn:
DMA destination address register
DMATCRn: DMA transfer count register
CHCRn: DMA channel control register
DMAOR: DMA operation register
DMARS0 to
DMARS2: DMA extended resource selector 0 to 2
DEIn:
DMA transfer-end interrupt request to the CPU
n:
0, 1, 2, 3, 4, 5
Figure 10.1 Block Diagram of DMAC
Rev. 3.00 Jan. 18, 2008 Page 408 of 1458
REJ09B0033-0300